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July 09, 2008
IRS2530D(S)
DIM8 IC Features
* * * * * * * * * * * * * * * * * * * * Dimming ballast control plus half-bridge driver Closed-loop lamp current dimming control Internal non-ZVS protection Internal crest factor protection Programmable preheat time Fixed dead-time (2.0s typ.) Lamp insert auto-restart Internal bootstrap MOSFET Internal 15.6V zener clamp diode on Vcc Micropower startup (250A) Latch immunity and ESD protection
TM
DIMMING BALLAST CONTROL IC
Product Summary
Topology VOFFSET VOUT IO+ & IO- (typical) Deadtime (typical) Half-Bridge 600 V VCC 180mA & 260mA 2.0s
Package Types
Ballast System Features
Single chip dimming solution Simple lamp current dimming control method Single lamp current sensing resistor required No half-bridge current-sensing resistor required No external protection circuits required (fully PDIP8 SO8 internal) Flash-free lamp start at all dimming levels Large reduction in component count Typical applications Easy to use for fast design cycle time * Linear dimming ballast (down to 10%) Increased manufacturability and reliability * 3-way dimming ballast * Multi-level switch dimming ballast
Typical Connection Diagram
L AC LINE INPUT N
F1
LF BR1
RVCC1
RVCC2
RLIM1 CF CBUS CVCC1 RLIM2
VCC
VB
1
8
RHO HO CBS CSNUB RLO MLS DCP2 RLMP2 RLMP1 CH2 CRES LRES:B CH1 MHS LRES:A CDC
IRS2530D
CVCC2 CDIM
COM
2
DIM
7 6 5
3
CVCO VCO
VS
SPIRAL CFL LAMP
4
CPH RVCO RDIM1 CFB
LO
(+) 1-10V DIM INPUT (-)
RFB DCP1 LRES:C
RDIM2 RCS
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Table of Contents
Description Qualification Information Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Input/Output Pin Equivalent Circuit Diagram Lead Definitions Lead Assignments State Diagram Application Information and Additional Details Package Details Tape and Reel Details Part Marking Information Ordering Information
Page
3 4 5 6 7 9 10 10 11 12 20 21 22 23
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Description
This IC takes full advantage of IR's patented ballast and high-voltage technologies to realize a simple, highperformance dimming ballast solution. A single high-voltage pin senses the half-bridge current and voltage to perform necessary ballast protection functions. The DC dim input voltage reference and the AC lamp current feedback have been coupled together allowing a single pin to be used for dimming. Combining these high-voltage control algorithms together with a simple dimming method in a single 8-pin IC results in a large reduction in component count, an increase in manufacturability and reliability, a reduced design cycle time, while maintaining high dimming ballast system performance
Block Diagram
Bootstrap MOSFET
VCC 1 UVLO COM 2
Driver Logic
8 High-Side Half-bridge Driver 7 6
VB HO VS
1uA VCO 4 Voltage Controlled Oscillator Fault Logic Crest Factor Protection Half-bridge Voltage Sensing
Dimming Control
Non-ZVS Protection Low-Side Half-bridge Driver 5 LO
DIM
3
Restart Logic
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Qualification Information
Qualification Level
Moisture Sensitivity Level
Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant
Industrial Comments: This family of ICs has passed JEDEC's Industrial qualification. IR's Consumer qualification level is granted by extension of the higher Industrial level. MSL2 SOIC8 (per IPC/JEDEC J-STD-020C) Not applicable PDIP8 (non-surface mount package style) Class C (per JEDEC standard EIA/JESD22-A115) Class 3A (per EIA/JEDEC standard JESD22-A114) Class I, Level A (per JESD78A) Yes
Qualification standards can be found at International Rectifier's web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information.
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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO VVCO VDIM ICC IOMAX dVS/dt PD PD RJA RJA TJ TS TL Definition High-Side Floating Supply Voltage High-Side Floating Supply Offset Voltage High-Side Floating Output Voltage Low-Side Output Voltage VCO Input Voltage DIM Input Voltage Supply Current Maximum allowable current at LO, HO and PFC due to external power transistor Miller effect. Allowable VS Pin Voltage Slew Rate Maximum Power Dissipation @ TA +25C, 8-Pin DIP Maximum Power Dissipation @ TA +25C, 8-Pin SOIC Thermal Resistance, Junction to Ambient, 8-Pin DIP Thermal Resistance, Junction to Ambient, 8-Pin SOIC Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds)

Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 ---500 -50 ---------55 -55 ---
Max. 625 VB + 0.3 VB + 0.3 VCC + 0.3 6 VCC + 0.3 20 500 50 1.0 0.625 85 128 150 150 300
Units
V
mA V/ns W C/W
C
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. This supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. This IC contains a zener clamp structure between the chip VCO and COM which has a nominal breakdown voltage of 7.25V. This pin should not be driven by a DC, low impedance power source greater than the VVCOMAX specified in the Electrical Characteristics section.
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Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. Symbol VBS VS VCC ICC VVCO TJ Definition High-Side Floating Supply Voltage Steady State High-Side Floating Supply Offset Voltage Supply Voltage Supply Current VCO Pin Voltage Junction Temperature Min. VCC - 0.7 -3.0
Max. VCLAMP 600 VCLAMP 5 6 125
Units V V V mA V C
VCCUV+ + 0.1V --0 -40
Care should be taken to avoid output switching conditions where the VS node decreases below COM by more than 5V.
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Electrical Characteristics
VCC=VBS=14V, VS=0V, CVCC=CBS=0.1F, CVCO=CDIM=10nF, CLO=CHO=1nF, and TA = 25C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective HO and LO output leads. Symbol Definition Min Typ Max Units Test Conditions
Low Voltage Supply Characteristics VCLAMP VCCUV+ VCCUVVCCUVHY IQCCUV ICCDIM IQCCFLT VVCOMAX IBS IQBSUV VBSUV+ VBSUVILK fMIN fMAX d DT IVCO VLOSD+ VLOSDVZVSTH VVCOFLT+ CSCF VCC Zener Clamp Voltage Rising VCC UVLO+ Threshold Falling VCC UVLO- Threshold VCC Undervoltage Lockout Hysteresis Micropower Startup VCC Supply Current DIM Mode VCC Supply Current Fault Mode VCC Supply Current VCO Pin Zener Clamp Voltage VBS Supply Current UVLO Mode VBS Quiescent Current Rising VBS Supply Undervoltage Threshold Falling VBS Supply Undervoltage Threshold Offset Supply Leakage Current Minimum Output Frequency Maximum Output Frequency Duty Cycle Output Deadtime (HO or LO) VCO Pin Charging Current LO Pin Shutdown Threshold LO Pin Re-start Threshold VS Non-ZVS Detection Threshold VCO Fault Rising Threshold Crest factor peak-to-average fault factor 14.6 11.5 9.5 1.5 ------------8.0 7.0 --15.6 12.5 10.5 2.0 250 4.5 375 7.25 2 --9.0 8.0 --16.6 13.5 11.5 3.0 --------3 50 10.0 V 9.0 50 A VB = VS = 600V VCO = 6V VCO = 0V MODE = ALL MODE = PH/IGN MODE = FAULT MODE = FAULT MODE = DIM, LO = HIGH MODE = PH/IGN N/A MODE = DIM VS offset = 0.5V A mA A V mA A VCC = 8V MODE = DIM MODE = FAULT MODE = DIM MODE = DIM VBS = 7V V ICC = 10mA
Floating Supply Characteristics
Ballast Control Characteristics 32.0 ------------------34.2 115 50 2.0 1 8.75 8.5 4.5 4.0 5.5 36.4 ------------------kHz % s A V
V
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Electrical Characteristics
VCC=VBS=14V, VS=0V, CVCC=CBS=0.1F, CVCO=CDIM=10nF, CLO=CHO=1nF, and TA = 25C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective HO and LO output leads. Symbol Definition Min Typ Max Units Test Conditions
Dimming Control Characteristics VDIMREG DIM Regulation Threshold --0.0 --V MODE = DIM
Gate Driver Output Characteristics (HO and LO) VOH VOL VOL_UV tr tf tSD IO+ IOHigh-Level Output Voltage Low-Level Output Voltage UV-Mode Output Voltage Output Rise Time Output Fall Time Shutdown Propagation Delay Output source current Output sink current ----------------VCC COM COM 120 50 350 180 260 ------220 80 ------mA ns IO = 0A IO = 0A IO = 0A, VCC VCCUV-
Bootstrap FET Characteristics VB_ON IB_CAP IB_10V VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on --30 8 13.3 55 12 ------V mA CBS = 0.1F VB = 10V
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I/O Pin Equivalent Circuit Diagrams
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Lead Definitions
Pin # 1 2 3 4 5 6 7 8 Symbol VCC COM DIM VCO LO VS HO VB IC power and signal ground Dimming DC reference and AC lamp current feedback input Voltage-controlled oscillator (VCO) input Half-bridge low-side gate driver output High voltage floating supply return and half-bridge sensing input High-side gate driver output High-side gate driver floating supply Description Logic and internal gate drive supply voltage
Lead Assignments
VCC
1
8
VB
IRS2530D
10
COM
2
7 HO
DIM
3
6 VS
VCO
4
5 LO
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IRS2530D(S)
State Diagram
Power Off
VCC > 0V
UVLO Mode
Half-Bridge Off
IQCCUV 250A VCO = 0V HO Off LO Open Circuit VCC > 12.5V (VCCUV+) and LO < 8.5V (VLOSD-) (Lamp Inserted) VCC < 10.5V (VCCUV-)
VCC < 10.5V (VCCUV-) or LO > 8.75V (VLOSD+) (Lamp Removed)
FAULT Mode
Fault Latch Set Half-Bridge Off IQCCUV 250A HO Off LO Open Circuit
VCO > 4.0V (VVCOFLT+) (Lamp non-strike)
PH/IGN Mode
Half-Bridge Oscillating Freq ramps from fMAX to fMIN VCO Charging (1A) non-ZVS Disabled Crest Factor Disabled
Lamp Ignites
CF > 5.5 (lamp removal)
DIM Mode
non-ZVS
ZVS
freq = freq + df
ZVS OK
Half-Bridge Oscillating @fDIM Dimming Loop Enabled non-ZVS Enabled Crest Factor Enabled
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Application Information and Additional Details
Information regarding the following topics is included as subsections within this section of the datasheet: * * * * * * * * UVLO Mode and IC Supply Circuitry Preheat/Ignition (PH/IGN) Mode Dim Mode Non Zero-Voltage Switching (ZVS) Protection Crest Factor Over-current Protection Fault Mode and Lamp Reset Component Selection PCB Layout Guidelines
UVLO Mode and IC Supply Circuitry The Under-Voltage Lock-Out Mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC, VCCUV+ (12.5 V, typical), and LO is above the shutdown threshold, VLOSD+ (8.75 V, typical). The UVLO circuit is designed to maintain an ultra-low supply current IQCCUV (<250 A), and to guarantee that the IC is fully functional before the high- and low-side output gate drivers are activated. The VCC capacitor, CVCC, is charged up from the DC bus voltage through supply resistors RVCC1 and RVCC2 (Figure 1). The values of these resistors are chosen such that VCC reaches the UVLO+ turn-on threshold voltage at the desired DC bus voltage level. Once the capacitor voltage on VCC reaches the start-up threshold, VCCUV+, the IC turns on and the HO and LO gate drive outputs start oscillating. The capacitor CVCC should be large enough to hold the voltage at VCC above the VCCUV- threshold until the external auxiliary supply can take over and supply the required voltage and current to the IC.
DCBUS(+)
RVCC1
RVCC2 DCP2
RLIM1 RLIM2 VCC 1 CVCC1 CVCC2 CDIM DIM REF and FB CVCO COM 2 DIM 3 VCO 4 VCC UVLO Bootstrap FET Driver 15.6V CLAMP Highand Lowside Driver VB 8 HO 7 VS 6 LO 5 RLO CBS RHO
MHS
TO LOAD
CSNUB
MLS
CPH RVCO DCP1
DCBUS(-)
LOAD RETURN
Figure 1, UVLO and supply circuitry. An external charge pump circuit consisting of capacitor CSNUB and diodes DCP1 and DCP2, comprises the auxiliary supply voltage for the low-side circuitry (Figure 1). To limit high peak currents that can flow from the external charge pump to VCC, a zener diode (18 V, typical) should be used for the lower charge pump diode, DCP1. Also, two low-ohmic resistors (RLIM1 and RLIM2, 10 each, typical) should be used together with CVCC1 and CVCC2 to further limit and filter fast current spikes to minimize resulting voltage spikes that can occur at VCC. An internal bootstrap MOSFET between VCC and VB and external supply capacitor, CBS, determine the supply voltage for the high-side driver circuitry (Figure 1). The bootstrap MOSFET is turned on when LO is `high' and charges CBS from VCC each cycle to maintain the VB-to-VS voltage above the VBSUVthreshold (8 V, typical). The value of CBS should be chosen such that the VB-to-VS voltage and ripple stays above VBSUV- at all times. When VCC exceeds VCCUV+ for the first time, LO will first oscillate for several cycles
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until the VB-to-VS voltage exceeds the high-side UVLO rising threshold, VBSUV+ (9 V, typical), and the highside driver is enabled. The capacitor CVCC should be large enough such that VCC does not reach UVLObefore HO is enabled and the charge pump supply takes over. External gate drive resistors, RHO and RLO, are also recommended as standard design practice to limit high peak currents that can flow into or out of the HO and LO gate drive outputs. During UVLO Mode, the high-side gate driver output, HO, is `low' and the VCO pin is pulled down internally to COM. The low-side gate driver output, LO, is open circuit and is used as a shutdown/reset input function for automatically restarting the IC when a lamp has been removed and re-inserted. The IC includes an internal shutdown threshold, VLOSD+ (8.75 V, typical), and re-start logic circuit at the LO pin that is only active during UVLO mode. If VCC is above VCCUV+, but the lamp is removed, the external pull-up network (RLMP1 and RLMP2) will pull LO above VLOSD+ and the IC will remain in UVLO mode. When the lamp is reinserted, the lower filament of the lamp will pull LO down below VLOSD- (8.5 V, typical) and the IC will exit UVLO Mode and enter Preheat/Ignition Mode.
Preheat/Ignition (PH/IGN) Mode When VCC exceeds VCCUV+ and the LO pin is below VLOSD-, the IC enters Preheat/Ignition Mode. An internal current source, IVCO (1 A, typical), (Figure 2) charges the external capacitor on pin VCO causing the voltage on pin VCO to start ramping up linearly. An additional quick-start current, IVCOQS (50 A, typical), is also connected to the VCO pin and charges the VCO pin initially to 0.85 V. The quick-start current charges the VCO voltage up quickly to the internal 1 to 5 V range of the internal VCO. When the VCO voltage exceeds 0.85 V the quick-start current is then disconnected internally and the VCO voltage continues to charge up with the normal frequency sweep current source, IVCO (1 A, typical) (Figure 3).
DCBUS(+)
RVCC1
RVCC2 DCP2
RLIM1 RLIM2 VCC 1 CVCC1 CVCC2 CDIM DIM REF and FB CVCO + _ Fault Logic COM 2 DIM 3 VCO 4 VCO 5 1uA Bootstrap FET Driver 15.6V CLAMP Highand Lowside Driver VB 8 HO 7 VS 6 LO RLO CBS RHO
MHS
TO LOAD
CSNUB
MLS 4.6V
CPH RVCO
DCP1
DCBUS(-)
LOAD RETURN
Figure 2, Preheat/Ignition Mode circuitry. The frequency ramps down from the maximum frequency towards the resonance frequency of the high-Q ballast output stage. The lamp filaments are preheated as the lamp voltage and load current increase. The voltage on pin VCO continues to increase and the frequency keeps decreasing until the lamp ignites. If the lamp ignites successfully, the IC will then enter DIM Mode (Figure 3).
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VVCO 4.0V VVCOFLT+
0.85V Preheat/Ignition Mode Freq fmax Dim Mode
fmin
VLAMP
Lamp Ignites
VDIM
DC dim reference
AC lamp current
Figure 3, Preheat/Ignition/Dim Mode timing diagram. The resonant output stage transitions to a series-L, parallel-RC circuit with the Q-value and operating point determined by the user dim level (Figure 4). If the lamp does not ignite, the voltage on pin VCO continues to increase and the frequency continues to decrease until the VCO voltage exceeds VVCOFLT+ (4.0V, typical) and the IC enters Fault Mode and shuts down. The minimum frequency should be set below the high-Q resonance frequency of the ballast output stage to ensure that the frequency ramps through resonance for lamp ignition (Figure 4). The desired preheat time can be set by adjusting the slope of the VCO ramp with the external capacitor, CPH.
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Vout Vin
High-Q
Ignition
10%
ea eh Pr t
50%
100%
Low-Q
Start
fmin f100% f50% f10%
fmax
Frequency
Figure 4, Resonant tank Bode plot with lamp dimming operating points.
Dim Mode When the lamp ignites, the ballast output stage becomes a series-L, parallel-RC circuit and the AC lamp current flows through the current sensing resistor, RCS. The resulting AC voltage across resistor RCS is coupled to the DIM pin through feedback resistor, RFB (1 k, typical), and feedback capacitor, CFB (0.1 F, typical). The DIM pin voltage is a combination of the DC offset voltage provided by the user dim setting and the AC voltage that is capacitively coupled through capacitor CFB from the lamp current sensing resistor to the DIM pin. The IC enters Dim Mode when the lamp ignites and the dimming control loop becomes active. The DC+AC voltage at the DIM pin is regulated by the control loop such that the valley of the AC voltage always stays at COM. By offsetting the AC voltage with a DC reference and holding the valley of the AC voltage at COM, the amplitude of the AC voltage, and therefore the AC lamp current, is accurately controlled. When the DC reference voltage at the DIM pin is decreased for dimming, the valleys of the AC voltage are pushed below COM. The dimming control circuit increases the frequency to decrease the AC lamp current until the AC valleys at the DIM pin are at COM again. When the DC reference is increased to increase the brightness level, the valleys of the AC voltage increase above COM. The dimming control circuit decreases the frequency to increase the AC lamp current until the AC valleys at the DIM pin are at COM again. In this way, the dimming control circuit keeps the AC lamp current peak-to-peak amplitude regulated to the desired value at all DC dim level settings. Capacitor CVCO programs the speed of the dimming loop and is typically set to a low value (2.2 nF, typical) for cycle-by-cycle lamp current control. An additional compensation network is formed by RVCO (1.5 k, typical) and CPH to prevent the VCO voltage from changing too much from one cycle to the next for maintaining smooth and stable dimming. A capacitor, CDIM (10 nF, typical) is also necessary from the DIM pin to COM for filtering high-frequency switching noise. During Dim Mode, the VS-sensing circuit and non-ZVS and crest factor protection circuits are also enabled (see State Diagram, Page 11).
Non Zero-Voltage Switching (ZVS) Protection During Dim Mode, if the voltage at the VS pin has not slewed entirely to COM during the dead-time such that there is voltage between the drain and source of the external low-side half-bridge MOSFET when LO turnson, then the system is operating too close to, or, on the capacitive side of resonance. The result is non-ZVS capacitive-mode switching that causes high peak currents to flow in the half-bridge MOSFETs that can damage or destroy them (Figure 5). This can typically occur during a decrease of the DC bus during an AC mains interrupt or brown-out condition, lamp variations over time, driving an incorrect lamp type, or component and temperature variations. To protect against this, an internal high-voltage MOSFET is turned on at each turn-off of HO and the VS-sensing circuit measures the VS voltage at each rising edge of LO. If the VS voltage is greater than VZVSTH (4.5 V, typical), the non-ZVS control circuit will increase the frequency until ZVS is reached again. Increasing the frequency due to non-ZVS during a brown-out also ensures that
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that the ignition/preheat ramp will be reset to re-ignite the lamp reliably in case the DC bus decreases too far and the lamp extinguishes.
LO HO
VS
!
I
L
I
MLS
!
I
MHS
!
Too close to resonance. Hard-switching and high peak MOSFET currents!
Frequency shifted higher to maintain ZVS.
Figure 5, Non-ZVS protection timing diagram.
Crest Factor Over-current Protection The IRS2530D uses the VS-sensing circuitry to also measure the low-side half-bridge MOSFET current for detecting an over-current fault. By using the RDSon of the external low-side MOSFET for current sensing, the IC eliminates the need for an external current sensing resistor. To cancel changes in the RDSon value due to temperature and MOSFET variations, the IC performs a crest factor measurement that detects when the peak current exceeds the average current by a factor of 5.5 (CSCF). Measuring the crest factor is ideal for detecting when the inductor saturates due to excessive current that occurs in the resonant tank when the frequency is too close to resonance. During Dim Mode, the crest factor over-current protection is used to detect if the filaments fail, the lamp is removed, or the lamp becomes deactivated. During each of these fault conditions, the output stage will transition to a series-LC configuration. The resonant inductor, LRES, and resonant capacitor, CRES, remain connected together to form a complete circuit due to the voltage-mode heating configuration to the lamp (see Typical Application Diagram, Page 1). The frequency will move towards resonance until the inductor saturates. The crest factor protection circuit will then detect the saturation and the IC will enter Fault Mode and shut down.
Fault Mode and Lamp Reset During Fault Mode the internal fault latch is set, HO is off, LO is open circuit, and the IC consumes an ultralow micro-power current (see State Diagram, Page 11). The IC can be reset with a lamp exchange (as detected by the LO pin) or a recycling of VCC below and back above the UVLO thresholds. During Fault Mode, the LO pin is open circuit and is used as an input pin for resetting the IC. If the lamp is removed, the external pull-up network at the lower lamp filament, RLMP1 and RLMP2 (see Typical Application Diagram, Page 1), will pull LO above VLOSD+ (8.75V, typical) and the IC will exit Fault Mode and enter UVLO mode. When the lamp is re-inserted, the lower filament of the lamp will pull LO down below VLOSD- (8.5V, typical) and the IC will exit UVLO Mode and enter Preheat/Ignition Mode and restart the lamp.
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Component Selection Proper design of the circuit schematic (see Typical Application Diagram, Page 1) and component selection is important for achieving proper ballast functionality and preventing problems. The following design procedure should be followed for determining the various programming and filtering component values: 1) Capacitor CPH programs the desired preheat/ignition time. CPH is charged up by an internal 1 A current source at the VCO pin. The value of CPH is determined by:
CPH =
IVCO t PH / IGN 1A t PH / IGN = VVCOFLT 4V
2) Capacitor CVCO programs the speed of the dimming feedback loop. To ensure smooth and stable dimming, CVCO should be small enough such that the dimming loop reacts to lamp current changes each switching cycle. The value of CVCO is typically fixed for most lamp types and is given as:
CVCO = 2.2nF
3) Resistor RVCO and capacitor CPH provide additional compensation of the dimming loop to prevent the VCO voltage from changing too much over a given switching cycle. The value of RVCO is typically fixed for most lamp types and is given as:
RVCO = 1.5k
4) Resistor RCS measures the lamp current for dimming. RCS should be kept small to minimize power losses but the peak voltage across RCS at the lowest lamp current dimming level should be above a minimum level to avoid noise problems. Using the minimum rms lamp current during dimming, a minimum allowable peak voltage level across RCS of 100 mV, and an additional factor of 5 (signal attenuation due to RFB and CDIM), the value of RCS is determined by:
RCS =
100mV I LAMP _ RMS _ MIN 2
x5
Using the maximum rms lamp current, the power loss in resistor RCS is then determined by:
PLOSS _ RCS = ( I LAMP _ RMS _ MAX ) 2 x RCS
5) The additional feedback components include RFB for current limiting and noise filtering, CFB for DC blocking, and CDIM for noise filtering. The value of these components are typically fixed for most lamp types and are given as:
R FB = 1k
C FB = 0.1F C DIM = 10nF
6) Capacitors CVCC2 and CBS are the low-side and high-side supply capacitors for maintaining their respective supply voltages and providing high-frequency noise filtering. These capacitors are typically fixed and are given as:
CVCC 2 = C BS = 0.1F
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Component Selection (continued) 7) Resistors RVCC1 and RVCC2 provide the micro-power supply current to VCC and therefore determine the AC line input voltage where the ballast first turns on. The value of these resistors is determined by:
RVCC1 + RVCC 2 =
VAC ON 2 - VCCUV + 250uA
8) The additional supply components include capacitor CVCC1 for holding up VCC until the charge pump takes over, charge pump capacitor CSNUB for providing VCC supply current, charge pump diodes DCP1 and DCP2, and limiting resistors RLIM1 and RLIM2 for preventing high currents from flowing into VCC. These components are typically fixed for most design and are given as:
CVCC1 = 1F C SNUB = 1nF / 1KV DCP1 = 18V / 500mW DCP 2 = 1N 4148
R LIM 1 = RLIM 2 = 10
9) Resistors RLMP1 and RLMP2 provide the necessary pull-up signal to the LO pin for detecting the removal and insertion of the lower lamp filament. Both of these resistor should be high-ohmic to minimize current flow from VCC and to minimize current flow from the low-side filament to the LO pin. These resistor values are typically fixed and are given as:
RLMP1 = 470 K R LMP 2 = 1M
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PCB Layout Guidelines Proper care should be taken when laying out a PCB board to minimize noise effects due to high-frequency switching and to ensure proper functionality of the IRS2530D.
IC and programming components CPH IC COM connects to Power GND at single point Dim Input (+) (-) CVCC1 RLIM1 VCC charge pump circuitry DCP2 DCP1 (+) DC Bus CSNUB MLS High-side GND (VS) connects to half-bridge mid-point at single point MHS High-voltage, high-current and high-frequency half-bridge output Half-Bridge Output (VS) (-) DC Bus RLIM2 RLO CBS RHO CDIM Lamp current sensing and feedback CFB RFB
Power Ground RCS Lamp Return Filament Sensing Adjacent COM trace for additional noise filtering of feedback signal.
RVCO CVCO
1
RVCC2
RLMP2 RLMP1
CVCC2
RVCC1
Figure 9, Typical through-hole and SMD single-layer PCB layout for Application Diagram, Page 1 (bottom copper layer shown from top view). The programming components for the IC should be connected to the IC COM pin and then connected to power ground at a single point (Figure 9). The lamp current sensing feedback components (RFB, CFB) should be kept as far away as possible from the high-voltage/high-frequency half-bridge components to prevent switching noise from distorting the lamp current feedback signal. Adjacent ground traces to the feedback signals can also help reduce switching noise. In general, the following guidelines should be followed during PCB board layout: 1) Place all IC supply capacitors (CVCC2, CBS) and as close as possible to their respective supply and return pins (CVCC, CBS). 2) Place all IC programming and filter components as close as possible between their respective pins and COM (CVCO, RVCO, CPH, CDIM, CFB, RFB). 3) Connect IC COM to power GND at one connection only. Do not route power GND through the programming components or IC COM! 4) Connect high-side gate-drive ground (VS) to half-bridge mid-point at one connection only. Do not route high-side power ground through the VS components or VS pin. 5) Connect the anode of charge pump diode DCP1 to power ground. Do not connect to IC COM. 6) Use gate resistors (RLO, RHO) between all gate driver outputs and the gate of their respective power MOSFETs. 7) Use zener diode (18 V, typical) for lower charge pump diode (DCP1) and limiting resistors and capacitors (RLIM1, CVCC1, RLIM2, CVCC2) to filter high current spikes that can cause large voltage spikes to occur on VCC.
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Package Details
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IRS2530D(S)
Tape and Reel Details: SOIC8N
LOADED TAPE FEED DIRECTION
B
A
H
D F C
NOTE : CONTROLLING DIM ENSION IN M M
E G
CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60
8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062
F
D C E B A
G
H
REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40
Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566
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(c) 2008 International Rectifier
21
IRS2530D(S)
Part Marking Information
Part number
IRSxxxxx
YWW ?
IR logo
Date code
Pin 1 Identifier
? P MARKING CODE Lead Free Released Non-Lead Free Released
? XXXX
Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 200-002
www.irf.com
(c) 2008 International Rectifier
22
IRS2530D(S)
Ordering Information
Standard Pack Base Part Number Package Type Form PDIP8 IRS2530D SOIC8N Tube/Bulk Tube/Bulk Tape and Reel Quantity 50 95 2500 IRS2530DPBF IRS2530DSPBF IRS2530DSTRPBF Complete Part Number
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR's Technical Assistance Center http://www.irf.com/technical-info/
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
www.irf.com
(c) 2008 International Rectifier
23

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